Executive brief
- ST is building capacity into a demand correction on purpose. Automotive and industrial customers over-ordered during the shortage and then de-stocked. Fabs take four years to build and thirty to depreciate, so the capex calendar cannot follow the order book.
- Two transitions run in parallel: 200 mm to 300 mm in silicon, and 150 mm to 200 mm in silicon carbide. Both are yield-and-equipment problems before they are volume problems, which is why process and equipment engineers are hired ahead of operators.
- The product portfolio, not the node, is the moat. Power discretes, analogue, microcontrollers, sensors and secure elements are long-lived, design-win-driven businesses where a socket won today ships for a decade.
- Silicon carbide is a bet with a visible risk. It is the right technology for high-voltage electrification and its adoption rate is hostage to electric-vehicle volumes and to Chinese substrate competition. Candidates should treat it as a bet, not a certainty.
- The footprint decides the career. Crolles and Grenoble mean advanced logic and FD-SOI; Agrate means 300 mm power and analogue; Catania means silicon carbide; Rousset and Tours mean established high-volume lines. These are not interchangeable labour markets.
Most coverage of STMicroelectronics is written in one of two registers: sovereignty triumphalism, in which European subsidies restore a lost industry, or cyclical gloom, in which falling revenue proves the strategy failed. Both miss the interesting thing about the company, which is that it is deliberately doing the opposite of what its short-term numbers suggest. Revenue has come down hard from the shortage-era peak, and capacity investment has continued. That is not confusion. It is what capital-intensive manufacturing looks like when management is planning for the decade rather than the quarter, and it has direct consequences for anyone deciding whether to build a career there.
Read the cycle before you read the job posting
The 2021–2022 semiconductor shortage taught automotive and industrial buyers to order defensively. They built inventory, and then they stopped buying while they consumed it. The resulting correction hit exactly the segments where ST is strongest (automotive microcontrollers, power discretes, industrial analogue) which is why the company's revenue fell steeply from its peak while its structural position did not change.
Three things follow, and they are the difference between an informed application and a naive one:
- Fab loading, not headline revenue, predicts hiring. A fab with unused capacity carries depreciation regardless. Management's job in a trough is to fill lines with new products and new customers, which means design-win and product-engineering roles are funded even while operational headcount is disciplined.
- Announced cost programmes are real and they reshape sites. ST has publicly committed to reshaping its manufacturing footprint and reducing structural cost over a multi-year horizon, consolidating older back-end and 150/200 mm activity as new 300 mm and 200 mm SiC capacity comes on line. Ask, in any interview, whether the site you are joining is on the receiving end of that transfer or the sending end.
- Design wins are the only forward indicator that matters. A socket won in an automotive platform this year ships in volume three to five years later. Product lines with strong recent wins hire through the trough; product lines living on legacy sockets do not.
What the company actually sells
| Product family | Where it ends up | Why it is defensible | Disciplines hired |
|---|---|---|---|
| Power discretes and modules (Si, SiC, GaN) | EV traction inverters, chargers, industrial drives, power supplies | Qualification cycles are long and switching costs are high once a platform is designed around a device | Device physics, packaging, thermal, reliability, application engineering |
| Automotive microcontrollers | Zonal and domain controllers, powertrain, body electronics | Functional-safety certification and toolchain lock-in make replacement expensive | Digital design, embedded software, safety (ISO 26262-class) engineering, validation |
| Analogue and mixed-signal | Everything with a sensor, a battery or a motor | Design skill is scarce and tacit; process portability is limited | Analogue design, layout, characterisation, test engineering |
| MEMS and sensors | Consumer devices, industrial monitoring, automotive | Co-designed mechanics and electronics with proprietary process steps | MEMS process, packaging, algorithm and firmware work |
| Secure elements and edge AI | Payment, identity, industrial IoT, secure edge inference | Certification schemes and long product lifecycles | Security engineering, cryptography, low-power ML, firmware |
| FD-SOI-based digital and RF | Low-power edge processing, RF front ends, automotive compute | Power efficiency per unit cost at mature nodes rather than raw density | Digital implementation, process integration, substrate and RF characterisation |
The two transitions that are actually driving recruitment
200 mm to 300 mm in silicon
A 300 mm wafer yields more than twice the die area of a 200 mm wafer, so per-die cost falls when the line is loaded. That is why capacity investment concentrates in 300 mm at Crolles and Agrate. The engineering work is not glamorous and it is where the shortage of people is: recipe transfer and re-qualification, tool matching across chambers, defect and particle reduction, metrology, and statistical process control tight enough that a mature product transferred from an old line performs identically on the new one. Customers will not accept "equivalent"; they require data.
150 mm to 200 mm in silicon carbide
Silicon carbide is a harder material to grow, cut and process than silicon, and the substrate is a large fraction of device cost. Moving to 200 mm substrates is the main lever on that cost, and it is a materials problem: crystal quality, basal-plane dislocations, wafer bow, thinner dies without cracking, and packaging that removes heat at high switching frequencies. ST's Catania campus is the European centre of this work, including substrate manufacturing rather than only device fabrication: a vertical-integration choice that matters strategically, because merchant SiC substrate supply is a competitive pressure point.
The honest caveat: SiC demand is coupled to electric-vehicle production rates, which have grown more slowly in Europe than planners assumed, and Chinese substrate and device suppliers have driven prices down aggressively. A career in SiC is a bet on high-voltage electrification winning on the timescale of a decade. That is a defensible bet. It is not a risk-free one, and anyone who presents it as such is selling.
Where sovereignty policy touches the payroll
The European Chips Act set an ambition to roughly double Europe's share of world semiconductor production by 2030, and member-state programmes in France and Italy have supported ST's capacity build directly, including the Crolles joint facility with GlobalFoundries and the Catania silicon-carbide campus. What a candidate should take from this is narrow and useful: public support is usually tranche-based and conditional on milestones. That means hiring in a subsidised ramp arrives in steps tied to construction and qualification gates, not in a smooth curve. When a recruiter says "we are hiring a thousand people", the correct question is over what period and against which gate.
Eleven roles, described by the work
- Process integration engineer: owns a module (etch, deposition, implant, litho) end to end and is accountable for its contribution to yield. The most transferable job in the industry.
- Yield and defect engineer: reads inline metrology and electrical test to find the cause of loss. Half statistics, half physics, and the highest-leverage role in a ramp.
- Equipment engineer: keeps tools matched and available. Undervalued by graduates and structurally short of people; tool availability is the binding constraint on output.
- Power device engineer: designs SiC, GaN and silicon devices against on-resistance, switching loss and avalanche robustness.
- Packaging and thermal engineer: the real limiter in power electronics: sintered attach, substrate materials, thermal cycling and lifetime prediction.
- Analogue and mixed-signal designer: long apprenticeship, scarce supply, high pay, and the least automatable design discipline in the industry.
- Embedded and functional-safety engineer: builds automotive MCU software and the safety argument that lets a customer certify a vehicle system.
- Test and product engineer: turns a working die into a shippable product: test coverage, binning, cost per second of tester time.
- Application engineer: sits between the customer's design team and the product line; the fastest way to learn why customers actually choose a part.
- Reliability and qualification engineer: runs accelerated stress campaigns and defends the data to automotive customers.
- Facilities and ultrapure utilities engineer: water, gases, chemicals, abatement and energy. Rarely discussed, impossible to run a fab without, and increasingly the subject of local environmental scrutiny.
Entry routes and progression
In France, the reliable routes in are apprenticeship contracts with a fab or an equipment supplier, a CIFRE industrial doctorate for process and device specialisation, and the equipment-vendor path: joining a tool supplier, learning the tool deeply, then moving to the fab that runs it. In Italy, the Catania and Agrate sites recruit through regional technical universities on a similar pattern. Technician routes through BTS and BUT programmes are in structural shortage and often lead to process-engineer positions within a few years, which candidates underestimate.
Publicly advertised ranges in French and Italian semiconductor manufacturing cluster around the mid-thirties to mid-forties of thousands of euros for graduate engineers, the fifties to seventies for four-to-eight-year process and design specialists, and materially above that for scarce analogue designers and recognised yield authorities. Shift premiums apply to 24/7 fab roles. Verify against the specific posting; these are observed ranges, not commitments.
Four risks a serious candidate should price
- Cyclicality with a long capex tail. Capacity added at the top of a cycle depreciates through the trough. That pressure is transmitted to cost programmes and site consolidation before it reaches product investment.
- Electrification pace risk. SiC volumes depend on EV ramp rates and on high-voltage architecture adoption. Slower adoption stretches the payback and slows hiring in the newest capacity.
- Price competition from Asian suppliers. Substrate and device pricing has moved faster than most European plans assumed. Cost engineering, not only performance, decides which lines stay loaded.
- Subsidy conditionality and site consolidation. Public funding is milestone-based, and footprint reshaping means some sites contract while others grow. Ask which side of that line your site sits on before you relocate.
Five signals worth tracking
- Quarterly gross margin and unused-capacity charges: the clearest read on fab loading, and therefore on hiring.
- 300 mm and 200 mm SiC qualification milestones: each qualification gate releases a hiring tranche.
- Automotive design-win announcements: the three-to-five-year forward indicator for product-line headcount.
- European Chips Act tranche disbursements: they set the pace of construction-linked recruitment.
- SiC substrate pricing and Chinese capacity additions: the variable most likely to change the SiC investment case.
What to do with this
If you want the most durable skills in the company, target process integration, yield or equipment engineering: they survive every cycle because they determine cost. If you want the highest ceiling and are willing to serve a long apprenticeship, target analogue design. If you want the frontier and can accept adoption-rate risk, target silicon carbide at Catania or power packaging. And in every case, ask two questions the marketing will not answer for you: is this site growing or consolidating, and what design wins fund this role.
Related reading: the Crolles 3 fab dossier, Soitec and the materials layer, High-NA EUV, and the semiconductor skills stack.